Independent random processes, each with the nonrational power spectralÄensity resulting from isotropic Rayleigh fading. This paper addresses the task of efficiently simulating several The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 m, four metal layer CMOS (3.3 Volts) technology. Next, we present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. We briefly discuss the system-level model, array architecture, and control processor. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications.
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